Interface integrated circuits for quantum computing

The main objective of this line consists of the construction and experimental validation of operating models of nanoscale CMOS devices in the cryogenic temperature range below 2 K and their use in the design and fabrication of basic cells and systems for the implementation of the control and readout blocks operating at 10 GHz necessary for the construction of functional quantum computers. All this, in addition to incorporating low-voltage, low-power design techniques in order not to exceed the current maximum cooling capacity in the cryogenic regime (500 µW/qubit).