Design and development of a chipset (ASIC) for the next generation of wireless communications in SATCOM and 5G.

Main reseacher

Santiago Celma Pueyo

Concepción Aldea Chagoyen

Start date

01-01-2021

End date

31-12-2023

Group

Division

Industrial Technologies

Ministerio de Economía y Competitividad (RTC2019-007039-7)